Hardware description languages (HDLs) exist that can be used to provide a hardware description of a circuit. Exemplary HDLs include the Very high-speed integrated circuit Hardware Description Language (VHDL) and VERILOG. After a designer specifies a circuit in HDL, the HDL hardware description may be readily implemented as hardware, such as an integrated circuit, using a standard implementation design flow. For example, the HDL description can be synthesized to gate-level abstraction, mapped, placed, and routed for a programmable logic device (PLD), such as a field programmable gate array (FPGA).
Presently, there is considerable interest in specifying a circuit using an imperative programming language description. Exemplary programming languages include C, C++, JAVA, MATLAB scripting language, and the like. Since standard implementation tools that process an HDL description into hardware are readily available, it is desirable to translate a programming language description of a circuit into a hardware description, such as an HDL description. Accordingly, there exists a need in the art for a method and apparatus that allows a designer to design a circuit in software fashion and have a tool map software objects to appropriate hardware components for instantiation in a hardware description, such as an HDL description.